Electromagnetic Simulation for the Modeling of Interconnects

For modern VLSI circuits the well known Moore's law is used to generate road maps describing the expectations for the next generations of integrated circuits in which downsizing is accompanied by increasing circuit complexity and increased die size. This will greatly affects clock speed, interconnects and wire length as illustrated figure 1 [1]. Modern VLSI chips are expected to operate with a 1 GHz clock frequency at the end of this century with a corresponding wire length exceeding 1 km per chip.